1. Field of Invention
The present invention pertains to the field of memory cell arrays. More particularly, this invention relates to memory structure and fabrication processes for reducing crosstalk between memory cells in a cross point memory array.
2. Background
Portable consumer devices are becoming more compact yet increasingly sophisticated, requiring inherent structure to generate and/or utilize increasing quantities of data. Digital devices, such as digital cameras, may require at least hundreds of megabytes (MB) of data storage either built into or attachable to the camera. To satisfy the needs of this type of data storage application, future storage memories should be relatively low in cost, extremely compact and have capacities of around 100 MB to one gigabyte (GB). The storage memory should also be low in power consumption, less than one watt, and have relatively rugged physical characteristics to cope with the portable battery-powered operating environment.
For archival storage, data need only be written to the memory once. Preferably, the memory should have a short access time, on the order of milliseconds, and a moderate transfer rate, such as one to two MB per second. Preferably, the storage memory should be capable of interfacing with a wide variety of industry standard platforms and modules.
An application for meeting this demand involves the use of write-once cross point memory devices. In cross point memory arrays, a matrix of memory elements are formed, each comprising a fuse or anti-fuse and a diode connected in series. The memory elements are formed by a plurality of semiconductor and passivation layers disposed between conductive lines or electrodes.
One application for utilizing write-once cross point memory arrays to provide high density archival storage in portable devices is described in co-pending U.S. patent application Ser. No. 09/875,356, filed Jun. 5, 2001, entitled xe2x80x9cWrite-Once Memoryxe2x80x9d, the disclosure of which is incorporated herein by reference. The memory system disclosed therein, referred to as portable inexpensive rugged memory (PIRM), provides high capacity write-once memory at low cost for archival storage. This result is realized in part by avoiding silicon substrates, minimizing process complexity and lowering area density. The memory system includes a memory module formed of a laminated stack of integrated circuit layers constructed on plastic substrates. Each layer contains a cross-point diode memory array. Sensing of the data stored in the array is carried out from a separate integrated circuit remote from the memory module.
Because PIRM memory is relatively inexpensive, users will likely accumulate a large number of PIRM modules with a variety of stored content. It is important to be able to fabricate and assemble memory modules by a straightforward and relatively inexpensive process to minimize the need for precision while maximizing information storage density and simplifying addressing, reading and writing functions.
In layered high-density memory modules, such as described above, the potential for current leakage or xe2x80x9ccrosstalkxe2x80x9d between adjacent memory cells is substantially increased. This problem can result in intolerable increases in error rates and power loss as current leaks between xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d memory cells, as well as along other potential crosstalk paths.
In FIG. 1, three schematic diagrams illustrate likely paths for leakage current, where the cross point diodes are formed by orthogonal electrode strips having amorphous silicon p-i-n layers between the strips and the anti-fuse is made by interfacing intrinsic amorphorous silicon with a metal with the ability to diffuse into the semiconductor to form a good contact, a xe2x80x9cdiffusive metalxe2x80x9d. In FIG. 1A, a grid of cross point memory electrodes 10 is shown. The bottom electrode strips 12-14 in the X direction are orthogonal to the top electrode strips 15-17 in the Y direction. The bottom electrode strips 12 to 14 are made of a conducting material, preferably metal, and the top electrode strips 15-17 are made of diffusive metal, such as silver. Alternate positive voltages, +V, and negative voltages, xe2x88x92V, are imposed on alternate electrode strips in both directions, as shown.
FIG. 1B is a cross-sectional view along the X axis of the central bottom X electrode 13 having a negative voltage, xe2x88x92V thereon. Top electrode 15 has negative voltage xe2x88x92V voltage, electrode 16 has a positive voltage, +V voltage and electrode 17 has a negative voltage, xe2x88x92V. Diodes 20-22 are formed between electrodes 15-17 and electrode 13 by three semiconductor p-i-n layers 23-25 deposited on electrode 13. A p+-doped layer 23 is deposited above an intrinsic i layer 24 which in turn overlays a n+-doped layer 25. Anti-fuses 26-28 are formed by a passivation layer 29 formed above diodes 20-22 and beneath the top electrodes 15-17.
A p+-doped layer is a semiconductor material such as silicon heavily doped with a p-type dopant, such as boron. Similarly an n+-doped layer is a semiconductor material such as silicon that is heavily doped with an n-type dopant, such as phosphorous. The xe2x80x9c+xe2x80x9d designation indicates that the material has been heavily doped to at least 1% concentration.
Bit-to-bit crosstalk occurs when an anti-fuse of an addressed element is open (without conducting connection) while a neighboring anti-fuse is conducting. One leakage path is from a conducting anti-fuse to the nearest neighbor diode. As shown in FIG. 1B, when anti-fuse 26 is conducting, a leakage current 25 flows from anti-fuse 26 through the p+-layer 23 to neighboring diode 21. The leakage current through the p+-layer is small since the p+-layer is usually very thin, on the order of 20 nanometers.
FIG. 1C is a cross-sectional view along the Y axis of the central top electrode 16 having a positive voltage, +V thereon. Bottom electrode 12 has a positive voltage, +V, electrode 13 has a negative voltage, xe2x88x92V, and electrode 14 has a positive voltage, +V, imposed thereon. Anti-fuses 31-33 are formed by electrode 16 and passivation layer 29. Diodes 34-36 are formed by p-i-n layers 23-25 and electrodes 12-14. When anti-fuse 31 is conducting, leakage current 37 can flow through p+-layer 23 to neighboring diode element 35. Again, since the p+-layer 23 is quite thin, the leakage current 37 is small. However, the leakage current 38 through the n+layer 24, from electrode 14 of diode 34 to electrode 13 of diode 35, is large and can be a significant factor. The n-type layers are usually thicker and have substantially less resistance than p+layers. In addition, electron mobility is greater than hole mobility, so current leakage is usually greater in n+-layers than in p+-layers.
Leakage current increases with the size of a memory array. FIG. 2 shows a graph giving estimated leakage current (1.E-0X means 10xe2x88x92x amps) as a function of memory array size (1.E+0Y means 10+y bits of memory). The estimations in the graph assume that the resistivity of phosphorous-doped amorphous silicon is about one kilo-ohm centimeter (Kxcexa9-cm), the thickness of the n+ layer is 100 nanometers, the voltage differences across the electrodes is 5 volts, and the line width equals the line spacing. When the size of a memory array exceeds one megabit (10+6 memory cells), the leakage current is greater than 0.1 milliamp (10xe2x88x924 amps), which is unacceptable for a memory array. This point is illustrated in FIG. 2 at point 39. At the present time, consumer units having at least 8 megabytes (64 megabits) of memory are not unusual. Thus, leakage current is a major problem in both existing and future memory arrays.
Others have attempted to construct various means for minimizing current leakage in memory arrays. One such structure is shown in companion patents, U.S. Pat. Nos. 4,698,900 and 5,008,722 (Esquivel), in which a cross point EPROM array has trenches to provide improved isolation and improved leakage current characteristics between adjacent buried n+ bitlines. The Esquivel fabrication process involves etching a trench into a single crystal silicon substrate after surface layers have been removed. The achievement of isolating complex three terminal EPROM transistor devices has unique requirements, not easily translated to other technologies, such as the thin film construction utilized for high-density, portable, inexpensive data storage.
Cross point memory arrays using thin film fabrication and two terminal diode devices present a greater challenge. As used herein, thin film fabrication means using a layer of semiconductor and associated barrier and conductive layers, less than or equal to a few micrometers in thickness, to build memory array devices. These thin film devices involve fabrication of memory cells on very thin substrates such as glass or plastic sheets, where isolation trenches in the substrate are not possible. Under such conditions, new methods and forms of fabrication are needed to minimize the crosstalk problem, which substantially increases with larger and more dense memory arrays.
Accordingly, there is a need for a cross point thin-film memory structure and fabrication process to minimize current leakage or crosstalk between memory cells. Such structure needs to be simple and easily constructed, preferably without additional critical steps or masking in the fabrication process. Isolation structures for thin-film memory cells also need to be realized using simple, low-cost fabrication that is compatible with large-area processing and high density memory construction.
The present invention provides a cross point memory array structure that implements a trench arrangement between adjacent rows of memory cells to provide isolation and minimize leakage current. A passivation material may be deposited in the trenches to increase the isolation between memory cell rows. The memory cells are preferably fabricated to each have a diode and anti-fuse in series between transverse electrodes. As used herein, xe2x80x9ctransverse electrodesxe2x80x9d means electrodes that intersect at some non-zero angle. The trenches are constructed between memory cell rows, with the trench depth preferably extending to the bottom of the n+-layer. The cells may be fabricated with the anti-fuse above a diode and the passivation material from the anti-fuse may extend into the trenches to provide the isolation material. Alternatively, the diode may be constructed above the anti-fuse so that the n+-layer is higher, to minimize the trench depth. The trenches are cut as part of the usual etching steps for conductors, so that no additional patterning steps are necessary. Moreover, the masking and etching processes are non-critical in nature, as described earlier.
In one embodiment of the preferred invention, a cross point memory array is fabricated on a substrate and has a plurality of memory cells, each memory cell including a diode and an anti-fuse. A first conducting material is disposed in separated discrete areas on the substrate to form a plurality of first electrodes. A second conducting material is disposed in separated discrete areas that are transverse to the discrete areas of the first electrodes and are spaced from the first electrodes to form a plurality of second electrodes having cross points relative to the first electrodes. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer between the first electrodes and the diodes forms a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells.
In another preferred embodiment, a process for fabricating a cross point memory array has a plurality of memory cells on a substrate, each memory cell including a diode and an anti-fuse. A first conducting material is deposited on the substrate to form a bottom electrode. A plurality of semiconductor layers is successively deposited over the bottom electrode. Portions of the first conducting material and the semiconductor layers are removed to form separate discrete areas of diodes and bottom electrodes extending in a first direction and having trenches extending in the first direction between adjacent diodes to provide a barrier against crosstalk between adjacent cells. A passivation material is deposited above the diodes along each diode discrete area and in the trenches to substantially follow the contour of the trenches. A second conducting material is deposited above the passivation material to form a plurality of top electrodes extending in a second direction transverse to the first direction of extension of the bottom electrodes, thereby providing the plurality of memory cells at the cross points of the top and bottom electrodes.
In another preferred embodiment, a process for fabricating a cross point memory array has a plurality of memory cells on a substrate, each memory cell including a diode and an anti-fuse. A first conducting material is deposited on the substrate to form a bottom electrode. A passivation material is deposited above the first conducting material. Portions of the first conducting material and the passivation material are removed to form strips extending in a first direction along the substrate. A plurality of semiconductor layers is deposited successively over the passivation material. A second conducting material is deposited on the plurality of semiconductor layers. Portions of the second conducting material and the semiconductor layers are removed to form separate strips of memory cells with top electrodes extending in a second direction transverse to the first direction of the bottom electrodes, thereby forming trenches extending in the second direction between adjacent memory cells to provide a barrier against crosstalk between adjacent cells.
In another preferred embodiment, a process is provided for fabricating a cross point memory array having a plurality of memory cells on a substrate, wherein each memory cell includes a diode disposed adjacent to one line electrode. The process comprises etching together in one fabrication step the boundaries extending along a first direction of each of the diodes and each of the line electrodes to form multiple rows of the diodes and the one line electrode extending in the first direction.
Other aspects and advantages of the present invention will become apparent from the following detailed description, which in conjunction with the accompanying drawings illustrates by way of example the principles of the present invention.